The present disclosure relates to integrated electronic circuit design, and more specifically, to systems and methods to optimize the operating range of an electronic circuit.
Circuit paths with timing criticality, along with other factors such as additional timing margins (guard banding), power limit, circuit limited yield (CLY), and process conditions, decide the overall maximum frequency limit of operation. There are a variety of techniques to improve the maximum frequency of operation by optimizing these parameters; however, every technique has its penalty in terms of circuit overhead, power, chip real estate, and cost.
The power optimum implementation for a particular function may vary depending on the performance (clock frequency) requirement, supply voltage, and process point. This limits power savings if a single function implementation must be used across multiple conditions.
On the other side, with increasing technological advancements, chip yield has become very challenging. With very stringent process conditions and associated parameters, chip design now have to be flexible to account for broader process conditions to achieve desired maximum frequency of operation, especially on microprocessors.
Electronic circuits are designed to obtain higher performance without an increase in energy usage. In the context of processors, the performance is usually limited by the critical paths, which can make the maximum frequency of operation. Processor supports variety of features to optimize its energy usage. Dynamic voltage and frequency slewing (DVFS) is one widely adopted feature to optimize energy usage. Energy scale feature uses DVFS technique to adjust voltage and frequency in order to support nominal, slow, and fast modes of processor operation. In fast mode, the processor frequency is increased from its nominal frequency and voltage is accordingly increased to support higher frequency of operation. So this increased performance comes with a power penalty.
In many applications, power constraints may prevent all functions on an integrated circuit from being powered on at any given time. Different workloads may require different functional blocks of an integrated circuit to be active. This phenomenon of “dark silicon” (portions of an integrated circuit that are powered down and inactive) is becoming more common. Deciding which functions to place on an integrated circuit to make optimum use of the available circuit area is difficult, as is the closely related issue of determining which circuits should be active and which powered down during any particular workload.
Considering the above-mentioned drawbacks, therefore a method is needed to optimize the operating range of an electronic circuit and also to address yield challenges.